The present invention relates to wafer probing and, more particularly, to probes and test structures for wafer probing with differential signals.
Integrated circuits (ICs) are economically attractive because large numbers of often complex circuits, for example microprocessors, can be inexpensively fabricated on the surface of a wafer or substrate. Following fabrication, individual dies, including one or more circuits, are separated or singulated and encased in a package that provides for electrical connections between the exterior of the package and the circuit on the enclosed die. The separation and packaging of a die comprises a significant portion of the cost of manufacturing the integrated circuit device and to monitor and control the IC fabrication process and avoid the cost of packaging defective dies, manufacturers commonly add electrical circuits or test structures to the wafer to enable on-wafer testing or “probing” to verify the characteristics of the integrated circuits before the dies are singulated.
A test structure typically includes a device-under-test (DUT), a plurality of metallic probe or bond pads that are deposited at the wafer's surface and a plurality of conductive vias that connect the bond pads to the DUT which is typically fabricated beneath the surface of the wafer. The DUT typically comprises a simple circuit that includes a copy of one or more of the basic elements of the integrated circuit, such as a single line of conducting material, a chain of vias or a single transistor. The circuit elements of the DUT are typically produced with the same process and in the same layers of the die as the corresponding elements of the integrated circuit. The ICs are typically characterized “on-wafer” by applying a test instrument generated signal to the test structure and measuring the response of the test structure to the signal. Since the circuit elements of the DUT are fabricated with the same process as the corresponding elements of the integrated circuit, the electrical properties of the DUT are expected to be representative of the electrical properties of the corresponding components of the integrated circuit.
At higher frequencies, on-wafer characterization is commonly performed with a network analyzer. The network analyzer comprises a source of an AC signal, commonly, a radio frequency (RF) signal, that is used to stimulate the DUT of a test structure. A forward-reverse switch directs the stimulating signals to one or more of the bond pads of the test structure. Directional couplers or bridges pick off the forward or reverse waves traveling to or from the test structure. These signals are down-converted by intermediate frequency (IF) sections of the network analyzer where the signals are filtered, amplified and digitized for further processing and display. The result is a plurality of s-parameters (scattering parameters), the ratio of a normalized power wave comprising the response of the DUT to a normalized power wave comprising the stimulus supplied by the signal source.
The preferred interconnection for communicating the signals between the signal source and the receiver of the network analyzer and the test structure is coaxial cable. The transition between the coaxial cable and the bond pads of the test structure is preferably provided by a movable probe having one or more conductive probe tips that are arranged to be co-locatable with the bond pads of the test structure. The network analyzer and the test structure can be temporarily interconnected by bringing the probe tips into contact with the bond pads of the test structure.
Integrated circuits typically comprise a ground plane at the lower surface of the substrate on which the active and passive devices of the circuit are fabricated. The terminals of transistors fabricated on a semi-conductive substrate are typically capacitively interconnected, through the substrate, to the ground plane. The impedance of this parasitic capacitive interconnection is frequency dependent and at higher frequencies the ground potential and the true nature of ground referenced (single ended) signals becomes uncertain.
Balanced devices are more tolerant to poor radio frequency (RF) grounding than single ended devices making them attractive for high performance ICs. Referring to FIG. 1, a differential gain cell 20 is a balanced device comprising two nominally identical circuit halves 20A, 20B. When biased, with a DC current source 22, and stimulated with a differential mode signal, comprising even and odd mode components of equal amplitude and opposite phase (Si+1 and Si−1) 24, 26, a virtual ground is established at the symmetrical axis 28 of the two circuit halves. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the stimulating signal. The quality of the virtual ground of a balanced device is independent of the physical ground path and, therefore, balanced or differential circuits can tolerate poor RF grounding better than circuits operated with single ended signals. The two waveforms of the differential output signal (So+1 and So−1) 30, 32 are mutual references providing greater certainty in determining the transition from one binary value to the other and permitting a reduction the voltage swing of the signal and faster transition between binary values. Typically, differential devices can operate at lower signal power and higher data rates than single ended devices. In addition, noise from external sources, such as adjacent conductors, tends to couple, electrically and electromagnetically, in the common mode and cancel in the differential mode. As a result, balanced or differential circuits have good immunity to noise including noise at even-harmonic frequencies since signals that are of opposite phase at the fundamental frequency are in phase at the even harmonics. Improved tolerance to poor RF grounding, increased resistance to noise and reduced signal power make differential devices attractive for operation at higher frequencies.
A DUT comprising a differential gain cell provides a basis for a test structure enabling high frequency, on-wafer evaluation of devices included in the marketable integrated circuits fabricated on the wafer. However, the impedance of the internal connections of the DUT's components are often frequency dependant complicating de-embedding of the DUT and affecting the accuracy of the testing. For example, the input and output of a differential gain cell, such as the differential gain cell 20, are commonly capacitively interconnected as a result of parasitic capacitance connecting the terminals of the cell's transistors. Parasitic capacitance 42 between the gate 38, 40 and the drain 34, 36, a result of diffusion of the drain dopant under the oxide of the gate, is intrinsic and typical of MOS transistors. As a result to the transistor's gain, a change in the gate voltage produces an even larger change in the voltage at the transistor's drain. The application of differing voltages at the terminals of the parasitic gate-to-drain capacitor (Cgd) causes the capacitor to behave as a much larger capacitance, a phenomenon known as the Miller effect. As a result, input impedance of the differential device varies substantially with frequency, producing instability in the operation of the differential device.
What is desired is a method and apparatus for testing a differential device that minimizes or eliminates the Miller effect.